1. Field of the Invention
The present invention relates to digital circuitry for computing devices. In particular, the present invention relates to adjusting power consumption of digital circuitry relative to the critical path circuit having the largest propagation delay error.
2. Description of the Prior Art
Reducing power consumption of digital circuitry in computing devices increases battery life in portable applications (such as cellular telephones, portable computers, digital cameras, and the like) in addition to increasing the overall reliability/longevity since reducing power consumption reduces the operating temperature and associated stress on the device. In some computing devices, the propagation delays through certain critical paths of the digital circuitry that must remain within prescribed thresholds for proper operation affect the power consumption of the device. For example, manufactures have imposed certain restrictions on process tolerances and supply voltages to ensure the propagation delays remain within an acceptable operating range under worst case operating conditions, such as worst case process deviation and highest ambient temperature. However, operating all of the computing devices at a predetermined supply voltage to account for worst case conditions leads to inefficient power consumption for the majority of the devices that could operate with acceptable performance using a lower supply voltage.
An alternative approach to achieving acceptable propagation delays is to limit the clocking frequency of the digital circuitry to ensure reliable performance under all operating conditions, such as process deviations and ambient temperature. Reducing the clocking frequency also reduces power consumption which is directly related to the switching frequency of the digital circuitry. However, for applications where limiting the clocking frequency leads to unacceptably slow performance, acceptable propagation delay is achieved by increasing the supply voltage.
Prior art techniques have been suggested for measuring the propagation delay through a critical path of the digital circuitry in order to adapt the supply voltage and/or the clocking frequency to adapt power consumption and/or operating speed of each individual device. FIG. 1A shows an overview of a typical prior art implementation for measuring the propagation delay of a critical path circuit 2 and adjusting the supply voltage and/or clock frequency 4 (see, for example, U.S. Pat. Nos. 6,157,247 and 6,535,735). Matched delay circuit 6 is included in the device which matches the operating characteristics of the critical path circuit 2. A periodic input signal 8 is applied to the matched delay circuit 6, wherein the output 10 of the matched delay circuit 6 is the periodic input signal 8 shifted by a phase proportional to the propagation delay of the critical path circuit 2. A phase comparator 12 measures the phase difference between the periodic input signal 8 and the output 10 of the matched delay circuit 6, wherein the phase difference generates a pulse width modulated (PWM) signal 14 having a duty cycle proportional to the propagation delay of the matched delay circuit 6. The PWM signal 14 is converted by conversion circuitry 16 into an analog signal 18 which is filtered by filter 20. The output of filter 20 is a DC control signal 22 applied to an adjustable supply voltage/clock circuit 24 which outputs the adjusted supply voltage and/or clock frequency 4 applied to both the critical path circuit 2 and the matched delay circuit 2. In this manner, the supply voltage and/or clock frequency 4 is adjusted to maintain a target propagation delay through the critical path circuit 2 thereby adapting the power consumption and/or operating speed of the device.
The above mentioned '735 patent also teaches that the digital circuitry may comprise multiple critical path circuits that may or may not be active depending on the operating mode of the computing device. Each critical path circuit generates a status signal indicating whether the circuit is active, and a selector circuit selects the critical path circuit having the longest propagation delay for controlling the supply voltage and/or clock frequency. The problem with this technique, however, is that the selector circuit must have a priori knowledge about the propagation delays of each critical path circuit, as well as the propagation delay of each critical path circuit during different operating modes when different subsets of circuits may be active. This places a burden on the circuit designers requiring testing and characterizing of each critical path circuit over the multiple operating modes of the device. This problem is exacerbated when different components of a very large scale digital circuit are designed by multiple design teams possibly working in different geographical locations. In addition, the worst case critical path circuit may change relative to process variations and/or environmental changes (e.g., ambient temperature) thereby requiring additional margin to ensure the actual worst case critical path circuit doesn't fail.
There is, therefore, a need to improve upon the current techniques for adjusting the supply voltage and/or clocking frequency of critical path circuitry in order to optimize power consumption and/or operating speed of computing devices, such as cellular telephones, portable computers, digital cameras, and the like.